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Vancouver, BC, Canada
August 27 & 28 - Co-Located Events, Tutorials, Labs & Lightning Talks
August 29-31 - Conference
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Wednesday, August 29 • 11:10am - 11:50am
Introducing Cache Pseudo-Locking to Reduce Memory Access Latency - Reinette Chatre, Intel

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Reading from cache is significantly faster than reading from memory. Latency sensitive applications thus greatly benefit from having critical data and/or instructions in the cache.
Cache Pseudo-Locking (building on top of Intel's Cache Allocation Technology (CAT)) is a new feature being enabled in the Linux kernel that pseudo-locks a region of memory into a reserved portion of cache that only serves cache hits. The Cache Pseudo-Locked memory is made accessible to user space where an application can map it into its virtual address space and thus have a region of memory with reduced average read latency.

In this presentation, Reinette Chatre will introduce Cache Pseudo-Locking, demonstrate its benefits, and discuss the interfaces she has been working while enabling this feature in the Linux kernel.

Speakers
RC

Reinette Chatre

Software Engineer, Intel
Reinette Chatre is a Software Engineer who has worked for Intel's Open Source Technology Center for more than 10 years. Currently she is focused on enabling Intel's Cache Pseudo-Locking in the Linux kernel. Previous Linux kernel contributions include participation in the initial enabling... Read More →


Wednesday August 29, 2018 11:10am - 11:50am
Room 109